Conventionally, package substrates are used as chip carriers and electrical interconnections for semiconductor packages. Wiring layouts in the substrates are to serve as electrical connections with signal electrodes, ground and power electrodes of chips. R.O.C. Patent No. 490818 entitled “substrate for semiconductor chip package” discloses a package substrate having a chip-attaching region. A ground ring and a power ring are formed on top surface of the substrate. A plurality of first contact pads and second contact pads are formed on bottom surface of the substrate for bonding solder balls. The first contact pads are located below the perimeter of ground ring and the power ring, and are divided into two groups. The first group of the first contact pads is electrically connected with the ground ring for connecting ground electrodes of the chip. The second group of the first contact pads is electrically connected with the power ring for connecting power electrodes of the chip. The second contact pads are arranged around the first contact pads so as to electrically connect signal electrodes of the chip.
In order to improve the electrical performance of a semiconductor package, the substrate includes at least one ground/power layer between the contact pads and the ground/power ring. A substrate using a multi-layer PWB is disclosed in R.O.C. Patent No. 434664 entitled “lead-bond type chip package and manufacturing method thereof”. The substrate includes an interlayer circuit board having pre-preg disposed thereon. The interlayer circuit board possesses a metal ground/power plane so as to connect the ground/power source. Nevertheless, when a plurality of through holes are massively formed on multi-layer substrate for electrically connecting with lead fingers (signal), the through holes can not electrically be connected with the ground/power plane by forming a plurality of openings in the ground/power plane. Therefore, each opening is round corresponding to each through hole in position, enables the through holes to electrically insulate against the ground/power plane. However, electrical performance of the package substrate will be imparied when the through holes in the ground/power plane are mass and in irregular distribution.